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this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 1 en29LV640 rev. c, issue date: 2007/01/23 features ? single power supply operation - full voltage range: 2.7 to 3.6 volts for read, erase and program operations ? low power cons umption (typical values at 5 mhz) - 9 ma typical active read current - 20 ma typical program/erase current - less than 1 a current in standby or automatic sleep mode. ? jedec standards compatible - pinout and software compatible with single- power supply flash standard ? manufactured on 0.18 m process technology ? flexible sector architecture: - one hundred and twenty-eight 32k-word / 64k-byte sectors. ? minimum 100k program/erase endurance cycles. ? high performance for program and erase - word program time: 8s typical - sector erase time: 500ms typical - chip erase time: 64s typical ? package options - 48-pin tsop - 48-ball fbga ? software features: ? sector group protection - provide locking of sectors to prevent program or erase operations within individual sectors - additionally, temporary sector group unprotect allows code changes in previously protected sectors. ? standard data# polling and toggle bits feature ? unlock bypass program command supported ? sector erase suspend / resume modes: read and program another sector during sector erase suspend mode ? support jedec common flash interface (cfi). ? hardware features: ? pin compatible to lower density, easy replacement for code expansion. ? reset# hardware reset pin - hardware method to reset the device to read mode. ? wp#/acc input pin - write protect (wp#) function allows protection of first or last 32k-word sector, regardless of previous sector protect status - acceleration (acc) function provides accelerated program times general description the en29LV640h/l / en29LV640u is a 64-megabit ( 4mx16 ), electrically erasable, read/write non- volatile flash memory. any word can be programmed typically in 8s. this device is entirely command set compatible with the jedec single-power-supply flash standard. the en29LV640h/l / en29LV640u is designed to allow either single sector or full chip erase operation, where each sector group can be protected against program/erase operations or temporarily unprotected to erase or program. the device can sustain a minimum of 100k program/erase cycles on each sector. en29LV640 64 megabit (4m x 16-bit ) cm os 3.0 volt-only, uniform sector flash memory
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 2 en29LV640 rev. c, issue date: 2007/01/23 product selector guide product number en29LV640h/l en29LV640u speed option full voltage range: v cc =2.7 ? 3.6 v 90 90 max access time (ns) 90 90 max ce# access time (ns) 90 90 max oe# access time (ns) 35 35 block diagram we# ce# oe# state control command register erase voltage generator input/output buffers program voltage generator chip enable output enable logic data latch y-decoder x-decoder y-gating cell matrix timer v cc detector a21-a0 v cc v ss dq15-dq0 address latch sector protect switches stb stb wp#/ acc ry/by# reset#
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 3 en29LV640 rev. c, issue date: 2007/01/23 connection diagrams
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 4 en29LV640 rev. c, issue date: 2007/01/23 table 1. pin description logic diagram dq15 ? dq0 a21 ? a0 we# ce# ry/by# oe# reset# wp# / acc pin name function a21-a0 22 address inputs dq15-dq0 16 data inputs/outputs ce# chip enable input oe# output enable input we# write enable input wp#/acc write protec t / acceleration pin ry/by# ready/busy status output reset# hardware reset input pin v cc supply voltage (2.7-3.6v) v ss ground nc not connected to anything
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 5 en29LV640 rev. c, issue date: 2007/01/23 ordering information en29LV640 h 90 t c p packaging content (blank) = conventional p = pb free temperature range i = industrial (-40 c to +85 c) c = commercial (0 c to +70 c) package t = 48-pin tsop b = 48-ball fine pitch ball grid array (fbga) 0.80mm pitch speed option see product selector guide and valid combinations sector for write protect (wp#/acc=0) h = highest address sector protected l = lowest address sector protected base part number en29LV640 / en29LV640u 64 megabit(4m x 16-bit) uniform sector flash 3v read, erase and program product selector guide valid combinations vcc en29LV640h C 90 en29LV640l C 90 ti, tc bi,bc v cc = 2.7v-3.6v
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 6 en29LV640 rev. c, issue date: 2007/01/23 table 2. sector (group) address tables sector group protect/unprotect sector address range for sector erase sector group a21-a17 sector a21 a20 a19 a18 a17 a16 a15 address range (hexadecimal) sa0 0 0 0 0 0 0 0 000000?007fff sa1 0 0 0 0 0 0 1 008000?00ffff sa2 0 0 0 0 0 1 0 010000?017fff sg0 00000 sa3 0 0 0 0 0 1 1 018000?01ffff sa4 0 0 0 0 1 0 0 020000?027fff sa5 0 0 0 0 1 0 1 028000?02ffff sa6 0 0 0 0 1 1 0 030000?037fff sg1 00001 sa7 0 0 0 0 1 1 1 038000?03ffff sa8 0 0 0 1 0 0 0 040000?047fff sa9 0 0 0 1 0 0 1 048000?04ffff sa10 0 0 0 1 0 1 0 050000?057fff sg2 00010 sa11 0 0 0 1 0 1 1 058000?05ffff sa12 0 0 0 1 1 0 0 060000?067fff sa13 0 0 0 1 1 0 1 068000?06ffff sa14 0 0 0 1 1 1 0 070000?077fff sg3 00011 sa15 0 0 0 1 1 1 1 078000?07ffff sa16 0 0 1 0 0 0 0 080000?087fff sa17 0 0 1 0 0 0 1 088000?08ffff sa18 0 0 1 0 0 1 0 090000?097fff sg 4 00100 sa19 0 0 1 0 0 1 1 098000?09ffff sa20 0 0 1 0 1 0 0 0a0000?0a7fff sa21 0 0 1 0 1 0 1 0a8000?0affff sa22 0 0 1 0 1 1 0 0b0000?0b7fff sg 5 00101 sa23 0 0 1 0 1 1 1 0b8000?0bffff sa24 0 0 1 1 0 0 0 0c0000?0c7fff sa25 0 0 1 1 0 0 1 0c8000?0cffff sa26 0 0 1 1 0 1 0 0d0000?0d7fff sg 6 00110 sa27 0 0 1 1 0 1 1 0d8000?0dffff sa28 0 0 1 1 1 0 0 0e0000?0e7fff sa29 0 0 1 1 1 0 1 0e8000?0effff sa30 0 0 1 1 1 1 0 0f0000?0f7fff sg7 00111 sa31 0 0 1 1 1 1 1 0f8000?0fffff
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 7 en29LV640 rev. c, issue date: 2007/01/23 sector group a21-a17 sector a21 a20 a19 a18 a17 a16 a15 address range (hexadecimal) sa32 0 1 0 0 0 0 0 100000?107fff sa33 0 1 0 0 0 0 1 108000?10ffff sa34 0 1 0 0 0 1 0 110000?117fff sg8 01000 sa35 0 1 0 0 0 1 1 118000?11ffff sa36 0 1 0 0 1 0 0 120000?127fff sa37 0 1 0 0 1 0 1 128000?12ffff sa38 0 1 0 0 1 1 0 130000?137fff sg9 01001 sa39 0 1 0 0 1 1 1 138000?13ffff sa40 0 1 0 1 0 0 0 140000?147fff sa41 0 1 0 1 0 0 1 148000?14ffff sa42 0 1 0 1 0 1 0 150000?157fff sg10 01010 sa43 0 1 0 1 0 1 1 158000?15ffff sa44 0 1 0 1 1 0 0 160000?167fff sa45 0 1 0 1 1 0 1 168000?16ffff sa46 0 1 0 1 1 1 0 170000?177fff sg11 01011 sa47 0 1 0 1 1 1 1 178000?17ffff sa48 0 1 1 0 0 0 0 180000?187fff sa49 0 1 1 0 0 0 1 188000?18ffff sa50 0 1 1 0 0 1 0 190000?197fff sg12 01100 sa51 0 1 1 0 0 1 1 198000?19ffff sa52 0 1 1 0 1 0 0 1a0000?1a7fff sa53 0 1 1 0 1 0 1 1a8000?1affff sa54 0 1 1 0 1 1 0 1b0000?1b7fff sg13 01101 sa55 0 1 1 0 1 1 1 1b8000?1bffff sa56 0 1 1 1 0 0 0 1c0000?1c7fff sa57 0 1 1 1 0 0 1 1c8000?1cffff sa58 0 1 1 1 0 1 0 1d0000?1d7fff sg14 01110 sa59 0 1 1 1 0 1 1 1d8000?1dffff sa60 0 1 1 1 1 0 0 1e0000?1e7fff sa61 0 1 1 1 1 0 1 1e8000?1effff sa62 0 1 1 1 1 1 0 1f0000?1f7fff sg15 01111 sa63 0 1 1 1 1 1 1 1f8000?1fffff
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 8 en29LV640 rev. c, issue date: 2007/01/23 sector group a21-a17 sector a21 a20 a19 a18 a17 a16 a15 address range (hexadecimal) sa64 1 0 0 0 0 0 0 200000?207fff sa65 1 0 0 0 0 0 1 208000?20ffff sa66 1 0 0 0 0 1 0 210000?217fff sg16 10000 sa67 1 0 0 0 0 1 1 218000?21ffff sa68 1 0 0 0 1 0 0 220000?227fff sa69 1 0 0 0 1 0 1 228000?22ffff sa70 1 0 0 0 1 1 0 230000?237fff sg17 10001 sa71 1 0 0 0 1 1 1 238000?23ffff sa72 1 0 0 1 0 0 0 240000?247fff sa73 1 0 0 1 0 0 1 248000?24ffff sa74 1 0 0 1 0 1 0 250000?257fff sg18 10010 sa75 1 0 0 1 0 1 1 258000?25ffff sa76 1 0 0 1 1 0 0 260000?267fff sa77 1 0 0 1 1 0 1 268000?26ffff sa78 1 0 0 1 1 1 0 270000?277fff sg19 10011 sa79 1 0 0 1 1 1 1 278000?27ffff sa80 1 0 1 0 0 0 0 280000?287fff sa81 1 0 1 0 0 0 1 288000?28ffff sa82 1 0 1 0 0 1 0 290000?297fff sg20 10100 sa83 1 0 1 0 0 1 1 298000?29ffff sa84 1 0 1 0 1 0 0 2a0000?2a7fff sa85 1 0 1 0 1 0 1 2a8000?2affff sa86 1 0 1 0 1 1 0 2b0000?2b7fff sg21 10101 sa87 1 0 1 0 1 1 1 2b8000?2bffff sa88 1 0 1 1 0 0 0 2c0000?2c7fff sa89 1 0 1 1 0 0 1 2c8000?2cffff sa90 1 0 1 1 0 1 0 2d0000?2d7fff sg22 10110 sa91 1 0 1 1 0 1 1 2d8000?2dffff sa92 1 0 1 1 1 0 0 2e0000?2e7fff sa93 1 0 1 1 1 0 1 2e8000?2effff sa94 1 0 1 1 1 1 0 2f0000?2f7fff sg23 10111 sa95 1 0 1 1 1 1 1 2f8000?2fffff
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 9 en29LV640 rev. c, issue date: 2007/01/23 sector group a21-a17 sector a21 a20 a19 a18 a17 a16 a15 address range (hexadecimal) sa96 1 1 0 0 0 0 0 300000?307fff sa97 1 1 0 0 0 0 1 308000?30ffff sa98 1 1 0 0 0 1 0 310000?317fff sg24 11000 sa99 1 1 0 0 0 1 1 318000?31ffff sa100 1 1 0 0 1 0 0 320000?327fff sa101 1 1 0 0 1 0 1 328000?32ffff sa102 1 1 0 0 1 1 0 330000?337fff sg25 11001 sa103 1 1 0 0 1 1 1 338000?33ffff sa104 1 1 0 1 0 0 0 340000?347fff sa105 1 1 0 1 0 0 1 348000?34ffff sa106 1 1 0 1 0 1 0 350000?357fff sg26 11010 sa107 1 1 0 1 0 1 1 358000?35ffff sa108 1 1 0 1 1 0 0 360000?367fff sa109 1 1 0 1 1 0 1 368000?36ffff sa110 1 1 0 1 1 1 0 370000?377fff sg27 11011 sa111 1 1 0 1 1 1 1 378000?37ffff sa112 1 1 1 0 0 0 0 380000?387fff sa113 1 1 1 0 0 0 1 388000?38ffff sa114 1 1 1 0 0 1 0 390000?397fff sg28 11100 sa115 1 1 1 0 0 1 1 398000?39ffff sa116 1 1 1 0 1 0 0 3a0000?3a7fff sa117 1 1 1 0 1 0 1 3a8000?3affff sa118 1 1 1 0 1 1 0 3b0000?3b7fff sg29 11101 sa119 1 1 1 0 1 1 1 3b8000?3bffff sa120 1 1 1 1 0 0 0 3c0000?3c7fff sa121 1 1 1 1 0 0 1 3c8000?3cffff sa122 1 1 1 1 0 1 0 3d0000?3d7fff sg30 11110 sa123 1 1 1 1 0 1 1 3d8000?3dffff sa124 1 1 1 1 1 0 0 3e0000?3e7fff sa125 1 1 1 1 1 0 1 3e8000?3effff sa126 1 1 1 1 1 1 0 3f0000?3f7fff sg31 11111 sa127 1 1 1 1 1 1 1 3f8000?3fffff note: the sizes of all sectors are 32k-word.
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 10 en29LV640 rev. c, issue date: 2007/01/23 user mode definitions table 3. bus operations operation ce# oe# we# reset# wp#/acc a21-a0 dq15-dq0 read l l h h l / h a b in b d b out b write l h l h (note 1) a b in b (note 3) b accelerated program l h l h v b hh b a b in b (note 3) b cmos standby v b cc b 0.3v x x v b cc b 0.3v h x high-z ttl standby h x x h l / h x high-z output disable l h h h l / h x high-z hardware reset x x x l l / h x high-z sector group protect (note 2) l h l v b id b h sa, a6=l, a1=h, a0=l (note 3) sector group unprotect (note 2) l h l v b id b h sa, a6=h, a1=h, a0=l (note 3) temporary sector group unprotect x x x v b id b h a b in b (note 3) l=logic low= v b il b , h=logic high= v b ih b , v b id b = v hh = 11 0.5v = 10.5 11.5v, x=don?t care (either l or h, but not floating!), sa =sector addresses (a21-a15), d b in b =data in, d b out b =data out, a b in b =address in notes: 1. if the system asserts v b il on the wp# / acc pin, the device disables program and erase functions in the first or last sector independent of whether those sectors were protected or unprotected; if the system asserts v b ih on the wp# /acc pin, the dev ice reverts to whether the first or last sector was previously prot ected or unprotected. if wp# / acc = v b hh b , all sectors will be unprotected. 2. please refer to ?sector group protection & un protection?, flowchart 6a and flowchart 6b. 3. d in or d out as required by command sequence, data polling, or sector protect algorithm. read mode the device is automatically set to reading array data after device power-up or hardware reset. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm after the device accepts an sector erase suspend command, the device enters the sector erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. after completing a
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 11 en29LV640 rev. c, issue date: 2007/01/23 programming operation in the sector erase suspend mode, the system may once again read array data with the same exception. see ?sector erase suspend/resume commands? for more additional information. the system must issue the reset command to re-enable the device for reading array data if dq5 goes high or while in the autoselect mode. see the ?reset command? for additional details. output disable mode when the oe# pin is at a logic high level (v b ih b ), the output from the device is disabled. the output pins are placed in a high impedance state. standby mode the device has a cmos-compatible standby mode, which reduces the b current to < 1a (typical). it is placed in cmos-compatible standby when the ce# pin is at v b cc b 0.5. reset# and byte# pin must also be at cmos input levels. the device also has a ttl-compatible standby mode, which reduces the maximum v b cc b current to < 1ma. it is placed in ttl-compatible standby when the ce# pin is at v b ih b . when in standby modes, the outputs are in a high-impedance state independent of the oe# input. automatic sleep mode the device has an automatic sleep mode, which minimizes power cons umption. the devices will enter this mode automatically when the states of address bus remain stable for t acc + 30ns. icc 4 in the dc characteristics table shows the current specification. with standard access times, the device will output new data when addresses change. writing command sequences to write a command or command sequence to program data to the device or erase data, the system has to drive we# and ce# to v b il , and oe# to v b ih b . the device has an unlock bypass mode to facilitate faster progra mming. once the device enters the unlock bypass mode, only two write cycles are required to program a word, instead of four. the system can also read the autoselect codes by entering the autoselect mode, which need the autoselect command sequence to be written. please refer to the ?command definitions? for all the available commands. autoselect identification mode the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on dq15?dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v b id b (10.5 v to 11.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in autoselect codes table. in addition, when verifying sector group protection, the sector group address must appear on the appropriate highest order address bits. refer to the corresponding sector address tables. the ?command definitions? table shows the remaining address bits that are don?t-care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq15?dq0. to access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the command definitions table. this method does not require v b id b . see
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 12 en29LV640 rev. c, issue date: 2007/01/23 ?command definitions? for details on using the autoselect mode. note that a reset command is required to return to read mode when the device is in the autoselect mode. table 4. autoselect codes (using high voltage, v b id b ) l=logic low= v b il b , h=logic high= v b ih b , v b id b =11 0.5v, x=don?t care (either l or h, but not floating!), sa=sector addresses note: 1. a8=h is recommended for manufacturing id check. if a manufacturing id is read with a8=l, the chip will output a configuration code 7fh. 2. a9 = v b id b is for hv a9 autoselect mode only. a9 must be vcc (cmos logic level) for command autoselect mode. reset#: hardware reset when reset# is driven low for t b rp b , all output pins are tristates. all commands written in the internal state machine are reset to reading array data. please refer to timing diagram for reset# pin in ?ac characteristics?. sector group protection & unprotection the hardware sector group protection feature disables both program and erase operations in any sector group. the hardware chip unprotection feature re-enables both program and erase operations in previously protected sector group. a sector group consists of four adjacent sectors that would be protected at the same time. please see table 2 which show the organization of sector groups. there are two methods to enable this hardware protection circuitry. the first one requires only that the reset# pin be at v id and then standard microprocessor timings can be used to enable or disable this feature. see flowchart 6a and 6b for the algorithm and figure 11 for the timings. when doing sector group unprotect, all the unprotected sector groups must be protected prior to any unprotect write cycle. the second method is for programming equipment. this method requires v id to be applied to both oe# and a9 pins and non-standard microprocessor timings are used. this method is described in a separate document, the datasheet supplement of en29LV640h/l ; en29LV640u, which can be obtained by contacting a representa tive of eon silicon solution, inc. description ce# oe# we# a21 to a15 a14 to a10 a9 p 2 p a8 a7 a6 a5 to a2 a1 a0 dq15 to dq0 h p 1 p xx1ch manufacturer id: eon l l h x x v b id b l xlxl l xx7fh autoselect device id l l h x x v b id b x x l x l h 227eh sector protection verification l l h sa x v b id b xxlxh l xx01h (protected) xx00h (unprotected)
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 13 en29LV640 rev. c, issue date: 2007/01/23 u write protect / accelerat ed program (wp# / acc) the write protect function provides a hardware method to protect the first or last sector against erase and program without using v id . when wp# is low, the device protects the first or last sector regardless of whether these sectors were previously protected or unprotected using the method described in ?sector group protection & unprotection?, program and erase operations in these sectors are ignored. when wp# is high, the device reverts to the previous protection status of the first or last sector. program and erase operations can now modify the data in those sectors unless the sector is protected using sector group protection. note that the wp# pin must not be left floating or unconnected. when wp#/acc is raised to v hh the memory automatically enters the unlock bypass mode(please refer to ?command definitions?), temporarily unprotects every protected sectors, and reduces the time required for program operation. the system would use a two-cycle program command sequence as required by the unlock bypass mode. when wp#/acc returns to v ih or v il , normal operation resumes. the transitions from v ih or v il to v hh and from v hh to v ih or v il must be slower than t b vhh b , see figure 5. note that the wp#/acc pin must not be left floating or unconnected. in addition, wp#/acc pin must not be at v hh for operations other than accelerated programming. it could cause the device to be damaged. never raise this pin to v hh from any mode except read mode, otherwise the memory may be left in an indeterminate state. a 0.1f capacitor should be connected between the wp#/acc pin and the vss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during unlock bypass program. temporary sector group unprotect this feature allows temporary unprotection of previously protected sector groups to change data while in-system. the temporary sector group unprotect mode is activated by setting the reset# pin to v b id b . during this mode, formerly protected sector groups can be programmed or erased by simply selecting the sector group addresses. once v b id b is removed from the reset# pin, all the previously protected sector groups are protected again. see accompanying flowchart and timing diagrams in figure 10 for more details. start reset#=v b id b b (note 1) b perform erase or program operations reset#=v b ih b temporary sector group un p rotect com p leted b ( note 2 ) notes: 1. all protected sector groups are unprotected. (if wp#/acc=v b il b , the first or last sector will remain protected.) 2. previously protected sector groups are protected again.
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 14 en29LV640 rev. c, issue date: 2007/01/23 common flash interface (cfi) the common flash interface (cfi) specification outlines device and host systems software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-i ndependent, jedec id- independent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h, any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 5-8.the upper address bits (a7?msb) must be all zeros. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode and the system can read cfi data at the addresses given in tables 5?8. the system must write the reset comm and to return the device to the autoselect mode. table 5. cfi query identification string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) table 6. system interface string addresses data description 1bh 0027h vcc min (write/erase) dq7-dq4: volt, dq3 ?dq0: 100 millivolt 1ch 0036h vcc max (write/erase) dq7-dq4: volt, dq3 ?dq0: 100 millivolt 1dh 0000h vpp min. voltage (00h = no vpp pin present) 1eh 0000h vpp max. voltage (00h = no vpp pin present) 1fh 0003h typical timeout per single byte/word write 2 p n p s 20h 0000h typical timeout for min, size buffer write 2 p n p s (00h = not supported) 21h 000ah typical timeout per individual block erase 2 p n p ms 22h 0000h typical timeout for full chip erase 2 p n p ms (00h = not supported) 23h 0005h max. timeout for byte/word write 2 p n p times typical 24h 0000h max. timeout for buffer write 2 p n p times typical 25h 0002h max. timeout per individual block erase 2 p n p times typical 26h 0000h max timeout for full chip erase 2 p n p times typical (00h = not supported)
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 15 en29LV640 rev. c, issue date: 2007/01/23 table 7. device geometry definition addresses data description 27h 0017h device size = 2 p n p bytes 28h 29h 0001h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 0000h 0000h max. number of byte in multi-byte write = 2 p n p (00h = not supported) 2ch 0001h number of erase block regions within device 2dh 2eh 2fh 30h 007fh 0000h 0000h 0001h erase block region 1 information (refer to the cfi specification of cfi publication 100) 31h 32h 33h 34h 0000h 0000h 0000h 0000h erase block region 2 information 35h 36h 37h 38h 0000h 0000h 0000h 0000h erase block region 3 information 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information table 8. primary vendor-specific extended query addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii 44h 0033h minor version number, ascii 45h 0004h address sensitive unlock 0 = required, 1 = not required 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0004h sector protect 0 = not supported, x = number of sectors in per group 48h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 0004h sector protect/unprotect scheme 01 = 29f040 mode, 02 = 29f016 mode, 03 = 29f400 mode, 04 = 29lv800a mode 4ah 0000h simultaneous operation 00 = not supported, 01 = supported 4bh 0000h burst mode type 00 = not supported, 01 = supported 4ch 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 00a5h minimum wp#/ acc (acceleration) supply voltage 00 = not supported, dq7-dq4 : volts, dq3-dq0 : 100mv 4eh 00b5h maximum wp#/ acc (acceleration) supply voltage 00 = not supported, dq7-dq4 : volts, dq3-dq0 : 100mv
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 16 en29LV640 rev. c, issue date: 2007/01/23 4fh 00xxh 00h = uniform sector devices
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 17 en29LV640 rev. c, issue date: 2007/01/23 hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the command definitions table. additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during vcc power up and power down transitions, or from system noise. low v b cc b write inhibit when v cc is less than v b lko b , the device does not accept any write cycles. this protects data during v cc power up and power down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until v cc is greater than v b lko b . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v b lko b . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v b il b , ce# = v b ih b , or we# = v b ih b . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. if ce#, we#, and oe# are all logical zero (not recommended usage), it will be considered a read. power-up write inhibit during power-up, the device automatically resets to read mode and locks out write cycles. even with ce# = v b il b , we#= v b il b and oe# = v b ih b , the device will not accept co mmands on the rising edge of we#.
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 18 en29LV640 rev. c, issue date: 2007/01/23 command definitions the operations of the device are selected by one or more commands written into the command register. commands are made up of data sequences written at specific addresses via the command register. the sequences for the specified operation are defined in the command definitions table (table 9). incorrect addresses, incorrect data values or improper sequences will reset the device to read mode. table 9. en29LV640h/l / en29LV640u command definitions bus cycles (note 1-2) 1 p st p cycle 2 p nd p cycle 3 p rd p cycle 4 p th p cycle 5 p th p cycle 6 p th p cycle command sequence cycles addr data addr data addr data addr data addr data addr data read (note 3) 1 ra rd reset 1 xxx f0 manufacturer id 4 555 aa 2aa 55 555 90 000 100 7f 1c device id 4 555 aa 2aa 55 555 90 x01 227e autoselect sector protect verify (note 4) 4 555 aa 2aa 55 555 90 (sa) x02 xx00 xx01 program 4 555 aa 2aa 55 555 a0 pa pd unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program 2 xxx a0 pa pd unlock bypass reset 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 sector erase suspend 1 ba b0 sector erase resume 1 ba 30 cfi query 1 55 98 address and data values indicated are in hex. unless specified, all bus cycles are write cycles ra = read address: address of the memory location to be read. this is a read cycle. rd = read data: data read from location ra during read operation. this is a read cycle. pa = program address: address of the memory location to be programmed. x = don?t-care pd = program data: data to be programmed at location pa sa = sector address: address of the sector to be erased or verified (in autoselect mode). address bits a21-a15 uniquely select any sector. notes: 1. data bits dq15-dq8 are don?t care in command sequences, except for rd and pd. 2. unless otherwise noted, address bits a21-a15 are don?t cares. 3. no unlock or command cycles required when device is in read mode. 4. the data is 00h for an unprotected sector group and 01h for a protected sector group.
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 19 en29LV640 rev. c, issue date: 2007/01/23 reading array data the device is automatically set to reading array data after power up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. following an sector erase suspend command, sector erase suspend mode is entered. the system can read array data using the standard read timings from sectors other than the one which is being erase-suspended. if the system reads at an address within erase-suspended sectors, the device outputs status data. after completing a programming operation in the sector erase suspend mode, the system may once again read array data with the same exception. the reset command must be issued to re-enable the device for reading array data if dq5 goes high during an active program or erase operation or while in the autoselect mode. see next section for details on reset. reset command writing the reset command to the device resets the device to reading array data. address bits are don?t-care for this command. the reset command may be written between the cycle sequences in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the cycle sequences in a program command sequence before programming begins. this resets the device to reading array data (also applies to programming in sector erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the cycle sequences in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data. if dq5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies in sector erase suspend mode). autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and devices id codes, and determine whether or not a sector group is protected. the command definitions table shows the address and data requirements. this is an alternative to the method that requires v b id b on address bit a9 and is intended for commercial programmers. two unlock cycles followed by the autoselect command initiate the autoselect command sequence. autoselect mode is then entered and the system may read at addresses shown in table 9 any number of times, without needing another command sequence. the system must write the reset command to exit the autoselect mode and return to reading array data. word programming command programming is performed by using a four-bus-cycle operation (two unlock write cycles followed by the program setup command and program data write cycle). when the program command is executed, no additional cpu controls or timings are necessary. an internal timer terminates the program operation auto matically. address is latche d on the falling edge of c e# or we#, whichever is last; data is latched on the rising edge of ce# or we#, whichever is first.
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 20 en29LV640 rev. c, issue date: 2007/01/23 any commands written to the device during the program operation are ignored. programming status can be checked by sampling data on dq7 (dat a# polling) or on dq6 (t oggle bit). when the program operation is successfully completed, the device returns to read mode and the user can read the data programmed to the device at that address. note that data can not be programmed from a ?0? to a ?1? . attempting to do so may halt the operation and set dq5 to ?1?, or cause the data# polling algorithm to indicate the operation was su ccessful. however, a succ eeding read will show that the data is still ?0?. only erase operations ca n convert a ?0? to a ?1?. when programming time limit is exceeded, dq5 w ill produce a logical ?1? and a reset command can return the device to read mode. programming is allowed in any sequence across sector boundaries. unlock bypass to speed up programming operation, the unlock bypass command may be used. once this feature is activated, the shorter two-cycle unlock bypass program command can be used instead of the normal four-cycle program command to program the device. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset command can be accepted. this mode is exited after issuing the unlock bypass reset command. the device powers up with this feature disabled the device provides accelerated program operations through the wp# / acc pin. when wp# / acc is asserted to v b hh b , the device automatically enters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. chip erase command chip erase is a six-bus-cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the command definitions table shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the embedded chip erase algorithm are ignored. the system can determine the status of the erase operation by using dq7, dq6, or dq2. see ?write operation status? for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. the command definitions table shows the address and data requirements for the sector erase command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. if there are several sectors to be erased, sector erase command sequences must be issued for each sector. that is, only a sector address can be specified for each sector erase command . users must issue another sector erase command for the next sector to be erased after the previous one is completed. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 21 en29LV640 rev. c, issue date: 2007/01/23 using dq7, dq6, or dq2. refer to ?write operation status? for information on these status bits. flowchart 4 illustrates the algorithm for the erase op eration. refer to the er ase/program operations tables in the ?ac characteristics? section for parameters, and to the sector erase operations timing diagram for timing waveforms. sector erase suspend / resume command the sector erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation. the sector erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. addresses are don?t-cares when writing the sector erase suspend command. when the sector erase suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. normal read and write timings and command definitions apply. please note that autoselect command sequence can not be accepted during sector erase suspend . reading at any address within erase-suspended sectors produces status data on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. see ?write operation status? for information on these status bits. after an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see ?write operation status? for more information. the autoselect command is not supported during sector erase suspend mode. the system must write the sector erase resume command (address bits are don?t-care) to exit the sector erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another sector erase suspend command can be written after the device has resumed erasing. write operation status dq7: data# polling the device provides data# polling on dq7 to indicate the status of the embedded operations. the data# polling feature is active during the prog ramming, sector erase, chip erase, and sector erase suspend. (see table 10) when the embedded programming is in progress, an attemp t to read the device will produce the complement of the data written to dq7. upon the completion of the programming operation, an attempt to read the device will pr oduce the true data written to dq7. data# polling is valid after the rising edge of the fourth we# or ce# pulse in the four-cycle sequence for program. when the embedded erase is in progress, an attemp t to read the device will produce a ?0? at the dq7 output. upon the completion of the embedded erase, the device will produce the ?1? at the dq7 output during the read cycl es. for chip erase or sector erase, data# polling is valid after the rising edge of the last we# or ce# pulse in the six-cycle sequence. data# polling must be performed at any address within a sector that is being programmed or erased and not a protected sector. otherwise, data # polling may give an ina ccurate result if the address used is in a protected sector.
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 22 en29LV640 rev. c, issue date: 2007/01/23 just prior to the completion of the embedded operations, dq7 may change asynchronously when the output enable (oe#) is low. this means that the device is driving status information on dq7 at one instant of time and valid data at the next instant of time. depending on the time the system samples the dq7 output, it may read the status of valid data. even if the device has completed the embedded operation and dq 7 has a valid data, the data output on dq0-dq 6 may be still invalid. the valid data on dq0-dq7 should be read on the subsequent read attempts. the flowchart for data# polling (d q7) is shown on flowchart 4. the data# polling (dq7) timing diagram is shown in figure 6. ry/by#: ready/busy status output the ry/by# is a dedicated, open-drain output pin that indicates whether an embedded algorithm is in progress or completed. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . in the output-low period, signifying busy, the device is actively erasing or programming. this includes programming in the erase suspend mode. if the output is high, signifying the ready, the device is ready to read array data (including during the erase suspend mode), or is in the standby mode. dq6: toggle bit i the device provides a ?toggle bit? on dq6 to indicate the status of the embedded programming and erase operations. (see table 10) during an embedded program or erase operation, successive attempts to read data from the device at any address (by active oe# or ce#) will result in dq6 toggling between ?zero? and ?one?. once the embedded program or erase op eration is completed, dq6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit is valid after the rising edge of the fourth we# pulse in the four-cycle sequence. during erase operation, the toggle bit is valid after the rising edge of the sixth we# pulse for sector erase or chip erase. in embedded progra mming, if the sector being written to is protected, dq6 will toggles for about 2 s, then stop toggling without the data in the sector having changed. in sector erase or chip erase, if all selected sectors are protected, dq6 will toggle for about 100 s. the chip will then return to the read mode without changing data in all protected sectors. the flowchart for the toggle bit (dq6) is shown in flowchart 5. the toggle bit timing diagram is shown in figure 7 . dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1.? this is a failure condition that indicates the program or erase cycle was not successfully completed. since it is possible that dq5 can become a 1 when the device has successfully completed its operation and has returned to read mode, the user must check again to see if the dq6 is toggling after detecting a ?1? on dq5. the dq5 failure condition may appear if the system tries to program a ?1? to a location that is previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the operation has exceeded the timing limits, dq5 produces a ?1.? under both these conditions, the system must issue the reset command to return the device to reading array data.
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 23 en29LV640 rev. c, issue date: 2007/01/23 dq3: sector erase timer after writing a sector erase command sequence, the output on dq3 can be checked to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) when sector erase starts, dq3 switches from ?0? to ?1?. this device does not support multiple sector erase (continuous sector erase) command sequences so it is not very meaningful since it immediately shows as a ?1? after the first 30h command. future devices may support this feature. dq2: erase toggle bit ii the ?toggle bit? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase- suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to the following table to compare outputs for dq2 and dq6. flowchart 6 shows the toggle bit algorithm, and the section ?dq2: toggle bit? explains the algorithm. see also the ?dq6: toggle bit i? subsection. refer to the toggle bit timings figure for the toggle bit timing diagram. the dq2 vs. dq6 figure shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to flowchart 5 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. however, after the initial two read cycles, the system determines that the toggle bit is still toggling. and the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operat ion. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data.
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 24 en29LV640 rev. c, issue date: 2007/01/23 write operation status operation dq7 dq6 dq5 dq3 dq2 ry/by# embedded program algorithm dq7# toggle 0 n/a no toggle 0 standard mode embedded erase algorithm 0 toggle 0 1 toggle 0 reading within erase suspended sector 1 no toggle 0 n/a toggle 1 reading within non-erase suspended sector data data data data data 1 sector erase suspend mode erase-suspend program dq7# toggle 0 n/a n/a 0 table 10. status register bits dq name logic level definition ?1? erase complete or erased sector in sector erase suspend ?0? erase on-going dq7 program complete or data of non-erased sector during sector erase suspend 7 data# polling dq7# program on-going ?-1-0-1-0-1-0-1-? erase or program on-going dq6 read during sector erase suspend 6 toggle bit ?-1-1-1-1-1-1-1-? erase complete ?1? program or erase error 5 error bit ?0? program or erase on-going ?1? erase operation start 3 sector erase time bit ?0? erase timeout period on-going ?-1-0-1-0-1-0-1-? chip erase, sector erase or read within erase- suspended sector. (when dq5=1, erase error due to currently addressed sector or program on erase-suspended sector 2 toggle bit dq2 read on addresses of non erase-suspend sectors notes: dq7: data# polling: indicates the p/e status check during prog ram or erase, and on completion before checking bits dq5 for program or erase success. dq6: toggle bit: remains at constant level when p/e operati ons are complete or erase suspend is acknowledged. successive reads output complementary data on dq6 while programming or erase operation are on-going. dq5: error bit: set to ?1? if failure in programming or erase dq3: sector erase command timeout bit: operation has started. only possible command is erase suspend (es). dq2: toggle bit: indicates the erase status and allows identification of the erased sector.
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 25 en29LV640 rev. c, issue date: 2007/01/23 embedded algorithms flowchart 1. embedded chip erase start write data aah to address 555h write data 55h to address 2aah write data 80h to address 555h write data aah to address 555h data poll from system data = ffh? erasure completed yes no write data 55h to address 2aah write data 10h to address 555h embedded chip erase in progress
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 26 en29LV640 rev. c, issue date: 2007/01/23 flowchart 2. embedded sector erase start write data aah to address 555h write data 55h to address 2aah write data 80h to address 555h write data aah to address 555h data poll from system data = ffh? erasure completed yes no write data 55h to address 2aah write data 30h to sector address last sector to erase? no yes embedded sector erase in progress
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 27 en29LV640 rev. c, issue date: 2007/01/23 flowchart 3. embedded program write data 55h to address 2aah write data a0h to address 555h write programmed data to destination address data poll from system verify ok? last address? program completed increment address yes no no yes embedded program in progress write data aah to address 555h start
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 28 en29LV640 rev. c, issue date: 2007/01/23 flowchart 4. data# polling algorithm notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be re-checked even if dq5 = ?1? in case the first set of reads was done at the exact instant when the status data was in transition. flowchart 5. toggle bit algorithm notes: 1. the system should be re-checked the toggle bit even if dq5 = ?1? in case the first set of reads was done at the exact instant when the status data was in transition. no no dq7 = data? dq5 = 1? dq7 = data? yes yes no yes read dq7-dq0 adr = va start read dq7-dq0 adr = va fail pass no yes dq6 = toggle? dq5 = 1? dq6 = toggle? no no yes yes read dq7-dq0 twice start read dq7-dq0 fail pass
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 29 en29LV640 rev. c, issue date: 2007/01/23 flowchart 6a. in-system sector group protect flowchart start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? no temporary sector group unprotect mode yes set up sector group address to protect: write 60h to sector group addr with a6 = 0, a1 = 1, a0 = 0 wait 150 s to verify: write 40h to sector group address with a6 = 0, a1 = 1, a0 = 0 read from sector address with a6 = 0, a1 = 1, a0 data = 01h? no plscnt = 25? increment plscnt no device failed yes protect another sector? yes reset plscnt = 1 no remove v id from reset# write reset command sector group protect complete sector group protect algorithm yes wait 0.4 s
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 30 en29LV640 rev. c, issue date: 2007/01/23 flowchart 6b. in-system sector group unprotect flowchart start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? temporary sector group unprotect mode no yes all sectors protected? yes no protect all sector groups: the indicated portion of the sector group protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address (see diagram 6a.) set up first sector g rou p address unprotect: write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 wait 15 ms verify unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 =0 read from sector group address with a6 = 1, a1 = 1, a0 = 0 data = 00h? no plsccnt = 1000? no increment plscnt yes device failed last sector group verified? no set up next sector group address remove v id from reset# write reset command sector group un p rotect com p lete sector group unprotect algorithm wait 0.4 s yes yes
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 31 en29LV640 rev. c, issue date: 2007/01/23 absolute maximum ratings parameter value unit storage temperature -65 to +125 c plastic packages -65 to +125 c ambient temperature with power applied -55 to +125 c output short circuit current p 1 p 200 ma v cc -0.5 to 4.0 v a9, oe#, wp#/acc and reset# p 2 p -0.5 to +11.5 v voltage with respect to ground all other pins p 3 p 0.5 to v cc + 0.5 v notes: 1. no more than one output shorted at a time. duration of the short circuit should not be greater than one second. 2. minimum dc input voltage on a9, oe#, reset# and wp#/acc pins is ?0.5v. during voltage transitions, a9, oe#, reset# and wp#/acc pins may undershoot v b ss b to ?1.0v for periods of up to 50ns and to ?2.0v for periods of up to 20ns. see figure below. maximum dc input voltage on a9, oe#, and reset# is 11.5v which may overshoot to 12.5v for periods up to 20ns. 3. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, inputs may undershoot v b ss b to ?1.0v for periods of up to 50ns and to ?2.0 v for periods of up to 20ns. see figure below. maximum dc voltage on output and i/o pins is v b cc b + 0.5 v. during voltage transitions, outputs may overshoot to v b cc b + 1.5 v for periods up to 20ns. see figure below. 4. stresses above the values so mentioned above may cause permanent damage to the device. these values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability. recommended operating ranges p 1 p parameter value unit ambient operating temperature commercial devices industrial devices 0 to 70 -40 to 85 c operating supply voltage v cc full voltage range:2.7 to 3.6v regulated voltage range:3.0 to 3.6v v 1.recommended operating ranges define those limits between which the functionality of the device is guaranteed. maximum negative overshoot maximum positive overshoot waveform waveform
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 32 en29LV640 rev. c, issue date: 2007/01/23 dc characteristics table 11. dc characteristics notes: 1. maximum i b cc b specifications are tested with v cc = v cc max. symbol parameter test conditions min typ max unit i b li b input leakage current 0v v b in b v cc 5 a i b lit b a9, wp#/acc input load current a9 = 11.5v 35 a i b lo b output leakage current 0v v b out b v cc 5 a i b cc1 b supply current (read) ce# = v b il b ; oe# = v b ih ; b f = 5mhz 9 16 ma i b cc2 b supply current (program or erase) ce# = v b il b , oe# = v b ih b , we# = v b il b 20 30 ma i b cc3 supply current (standby - cmos) ce# = byte# = reset# = v cc 0.3v (note 1) 1 5.0 a i b cc4 b reset current reset# = v ss 0.3v 1 5.0 ma i b cc5 b automatic sleep mode v b ih b = v cc 0.3v v b il b = v ss 0.3v, wp#/acc = v b ih 1 5.0 ua v b il b input low voltage -0.5 0.8 v v b ih b input high voltage 0.7 x v cc vcc 0.3 v v b hh b voltage for wp#/acc program acceleration 10.5 11.5 v v b id b voltage for autoselect or temporary sector unprotect 10.5 11.5 v v b ol b output low voltage i b ol b = 4.0 ma 0.45 v output high voltage ttl i b oh b = -2.0 ma 0.85 x v cc v v b oh b output high voltage cmos i b oh b = -100 a, v cc - 0.4v v v b lko b supply voltage (erase and program lock-out) 2.3 2.5 v
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 33 en29LV640 rev. c, issue date: 2007/01/23 test conditions test specifications . key to switching waveforms test conditions 90 unit output load 1 ttl gate output load capacitance, c b l b 30 pf input rise and fall times 5 ns input pulse levels 0.0-3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 0.5v io v device under test c l 6.2 k 2.7 k 3.3 v note: diodes are in3064 or equivalent
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 34 en29LV640 rev. c, issue date: 2007/01/23 ac characteristics table 13. read-only operations characteristics parameter symbols speed options jedec standard description test setup 90 unit t b avav b t b rc b read cycle time min 90 ns t b avqv b t b acc b address to output delay ce# = v b il oe# b b = b b v b il b max 90 ns t b elqv b t b ce b chip enable to output delay oe# b b = v b il b max 90 ns t b glqv b t b oe b output enable to output delay max 35 ns t b ehqz b t b df b chip enable to output high z max 20 ns t b ghqz b t b df b output enable to output high z max 20 ns t b axqx b t b oh b output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns read min 0 ns t b oeh b output enable hold time toggle and data# polling min 10 ns figure 2. ac waveforms for read operations addresses ce# oe# we# outputs reset# output valid t rc t acc t oe t ce t oeh t oh t df high z addresses stable
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 35 en29LV640 rev. c, issue date: 2007/01/23 ac characteristics hardware reset (reset#) table 12. hardware reset operations characteristics parameter description all speed options unit t b ready b reset# pin low to read or write embedded algorithms max 20 s t b ready b reset# pin low to read or write non embedded algorithms max 500 ns t b rp b reset# pulse width min 500 ns t b rh b reset# high time before read min 50 ns figure 1. ac waveforms for reset# reset# timings t rh t rp t ready ce# oe# reset# reset timings not during automatic algorithms t ready t rh t rp ce# oe# reset# reset timings during automatic algorithms
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 36 en29LV640 rev. c, issue date: 2007/01/23 ac characteristics table 14. write (erase/program) operations parameter symbols speed options jedec standard description 90 unit t b avav b t b wc b write cycle time min 90 ns t b avwl b t b as b address setup time min 0 ns t b wlax b t b ah b address hold time min 40 ns t b dvwh b t b ds b data setup time min 40 ns t b whdx b t b dh b data hold time min 0 ns t b oeh b output enable hold time during toggle and data# polling min 20 ns t b ghwl b t b ghwl b read recovery time before write (oe# high to we# low) min 0 ns t b elwl b t b cs b ce# setup time min 0 ns t b wheh b t b ch b ce# hold time min 0 ns t b wlwh b t b wp b write pulse width min 30 ns t b whdl b t b wph b write pulse width high min 25 ns t b whwh1 t b whwh1 b programming operation typ 8 s t b whwh1 b t b whwh1 b accelerated programming operation typ 5 s t b whwh2 b t b whwh2 b sector erase operation typ 0.5 s t b whwh3 b t b whwh3 b chip erase operation typ 64 s t b vhh b v hh rise and fall time min 250 ns t b vcs b v cc setup time min 50 s
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 37 en29LV640 rev. c, issue date: 2007/01/23 ac characteristics table 15. write (erase/program) operations alternate ce# controlled writes parameter symbols speed options jedec standar d description 90 unit t b avav b t b wc b write cycle time min 90 ns t b avel b t b as b address setup time min 0 ns t b elax b t b ah b address hold time min 40 ns t b dveh b t b ds b data setup time min 40 ns t b ehdx b t b dh b data hold time min 0 ns t b ghel b t b ghel b read recovery time before write (oe# high to ce# low) min 0 ns t b wlel b t b ws b we# setup time min 0 ns t b ehwh b t b wh b we# hold time min 0 ns t b eleh b t b cp b ce# pulse width min 45 ns t b ehel b t b cph b ce# pulse width high min 20 ns t b whwh1 b t b whwh1 b programming operation typ 8 s t b whwh1 b t b whwh1 b accelerated programming operation typ 5 s t b whwh2 b t b whwh2 b sector erase operation typ 0.5 s
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 38 en29LV640 rev. c, issue date: 2007/01/23 ac characteristics figure 3. ac waveforms for chip/sector erase operations timings notes: 1. sa=sector address (for sector erase) , va=valid address for reading status, d b out b =true data at read address. 2. v b cc b is shown only to illustrate t b vcs b measurement references. it cannot occur as shown during a valid command sequence. t dh t ds t busy t wph t ch t wp t cs t vcs t rb t wc t as t ah t ghwl t whwh2 or t whwh3 0x2aa sa va va 0x55 0x30 status d out addresses ce# oe# we# data ry/by# v cc 0x555 for chip erase erase command sequence (last 2 cycles) read status data (last two cycles)
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 39 en29LV640 rev. c, issue date: 2007/01/23 figure 4. program operation timings notes: 1. pa=program address, pd=program data, d b out b is the true data at the program address. 2. v b cc b shown in order to illustrate t b vcs b measurement references. it canno t occur as shown during a valid command sequence. figure 5. accelerated program timing diagram ac characteristics t vcs t dh t rb t whwh1 t busy t ds t cs t wph t ch t wp t ghwl t wc t as t ah 0x555 pa pa pa pd status d out oxa0 addresses ce# oe# we# data ry/by# v cc program command sequence (last 2 cycles) program command sequence (last 2 cycles) 0 or 3 v wp#/acc t b vhh b t b vhh b t b rsp b v b hh b 0 or 3 v ce# we#
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 40 en29LV640 rev. c, issue date: 2007/01/23 figure 6. ac waveforms for /data po lling during embedded algorithm operations notes: 1. va = valid address for reading data# polling status data 2. this diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cy cle. figure 7. ac waveforms for toggle bit during embedded algorithm operations t oeh t df t oh t busy t oe complement status data comple- ment true true status data valid data valid data t ce t acc t ch t rc va va va addresses ce# oe# we# dq[7] dq[6:0] ry/by# t rc t acc t ce t oe t oeh t ch t df t oh t busy va va va va valid status valid status valid status valid data (first read) (second d) (stops toggling) addresses ce# oe# we# dq6, dq2 ry/by#
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 41 en29LV640 rev. c, issue date: 2007/01/23 figure 8. alternate ce# controlled write operation timings notes: pa = address of the memory location to be programmed. pd = data to be programmed at byte address. va = valid address for reading program or erase status d b out b = array data read at va shown above are the last two cycles of the program or erase command sequence and the last status read cycle resett# shown to illustrate t b rh b measurement references. it cannot occur as shown during a valid command sequence. figure 9. dq2 vs. dq6 we# dq6 dq2 enter embedded erase erase suspend enter erase suspend program erase resume erase enter suspend read enter suspend program erase erase complete erase suspend read t wc t rh t as t ah t wh t ghel t cph t cp t ws t dh t ds t busy t cwhwh1 / t cwhwh2 / t cwhwh3 status d out 0xa0 for program pd for program 0x30 for sector erase 0x10 for chip erase va addresses we# oe# ce# data ry/by# reset# pa for program sa for sector erase 0x555 for chip erase 0x555 for program 0x2aa for erase
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 42 en29LV640 rev. c, issue date: 2007/01/23 ac characteristics temporary sector group unprotect speed option unit parameter std description 90 t b vidr b v b id b rise and fall time min 500 ns t b vihh b v b hh b rise and fall time min 500 ns t b rsp b reset# setup time for temporary sector unprotect min 4 s figure 10. temporary sector group unprotect timing diagram ac characteristics figure 11. sector group protect and unprotect timing diagram notes: use standard microprocessor timings for this device for read and write cycles. for sector group protect, use a6=0, a1=1, a0=0. for sector group unprotect, use a6=1, a1=1, a0=0. 0 or 3 v reset# t vidr t vidr t rsp v id 0 or 3 v ce# we# v id sa, a6,a1,a0 reset# 0v t vidr t vidr >1
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 43 en29LV640 rev. c, issue date: 2007/01/23 erase and program performance limits parameter typ max unit comments sector erase time 0.5 10 sec chip erase time 64 sec excludes 00h programming prior to erasure word programming time 8 300 s accelerated word program time 5 120 s chip programming time 20 60 sec excludes system level overhead erase/program endurance 100k cycles minimum 100k cycles note: typical conditions are room temperature, 3v and checkboard pattern programmed. latch up characteristics parameter description min max input voltage with respect to v b ss b on all pins except i/o pins (including a9, reset and oe#) -1.0 v 12.0 v input voltage with respect to v b ss b on all i/o pins -1.0 v v cc + 1.0 v v cc current -100 ma 100 ma note: these are latch up characteristics and the device sh ould never be put under these conditions. refer to absolute maximum ratings for the actual operating limits. 48-pin tsop package capacitance parameter symbol parameter description test setup typ max unit c b in b input capacitance v b in b = 0 6 7.5 pf c b out b output capacitance v b out b = 0 8.5 12 pf c b in2 b control pin capacitance v b in b = 0 7.5 9 pf note: test conditions are temperature = 25c and f = 1.0 mhz. data retention parameter description test conditions min unit 150c 10 years minimum pattern data retention time 125c 20 years
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 44 en29LV640 rev. c, issue date: 2007/01/23 figure 12. tsop 12mm x 20mm
this data sheet may be revised by subsequent versions ?2005 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 45 en29LV640 rev. c, issue date: 2007/01/23 revisions history revision no description date a initial release 2005/10/04 b correct tsop package outline drawing 2005//10/24 c revised cfi information at table 7. device geometry definition , page 15 1. addresses 2ch : data 0002h to 0001h 2. addresses 2dh : data 0007h to 007fh 3. addresses 2fh : data 0020h to 0000h 4. addresses 30h : data 0000h to 0001h 5. addresses 31h : data 007eh to 0000h 6. addresses 34h : data 0001h to 0000h 2007/1/23

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